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Technologies

 

MEMS technology is based on Silicon wafer processing using classical semiconductor processes and customized MEMS processes

 

Semicondutor processes

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Thin film deposition (to create conductive, isolating or sacrificial layers, mirrors, etc.)

•  Photolithography (to create pattern to be machined)

•  Surface micro-machining (to create thin structures above the surface)

 

 

 

 

 

Custom MEMS processes

•  Wet chemical etching (KOH) or deep reactive ion etching (DRIE) (to create bulk micro structures)

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Wafer-to-wafer stacking and bonding (functionality combined with wafer scale packaging)

 

 Some definitions:

 

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Micro electro-mechanical systems (MEMS)...

are micro-mechanical structures defined principally in silicon or glass materials. These devices can combine mechanical and/or optical and/or fluidic and electrical elements to provide basic sensing or actuating functions

• 

Microsystems (MST)...

are MEMS devices integrated with control electronics, packaged and tested to create a complete sensor or actuator

•  Hybrid microsystems...
are the combination of a MEMS device with other discrete IC devices mounted on a substrate
• 
Monolithic microsystems
are standard CMOS IC devices with MEMS functions integrated into the chip

 

 

Bulk micromachining

 

Surface micromachining Wafer stacking

 

•  Used to build mechanical structures where the functionality of the devices are defined within the depth of the wafer (membranes, valves, cantilevers)

•    Encompasses all techniques allowing material to be removed from the ‘bulk’ of a substrate (e.g. silicon, quartz, silicon on insulator, glass), such as anisotropic wet etching and deep reaction etching

•  True 3-dimensional design potential gives benefits especially for ‘precision’ applications
•  Distinct processing tools and skills required

 

•  Used to build mechanical features (cantilevers, free moving structures) on the surface of a substrate wafer (e.g. silicon, quartz, glass, polymer etc)
•  Successive deposition of sacrificial layers, removal of such layers by etching to release produced structures
•  Processes not largely dissimilar to classical semiconductor processes
•   Commonly integrated with IC process to produce monolothic MEMS
•  Limitations in product performance & stability

 

•  Used for vacuum level hermetic wafer-scale packaging

•  Two or more wafers of the same or different materials are bonded together
– Three level silicon sandwich
– Two level: silicon cap on ‘thick’ 
   SOI

•  Use of heat and pressure (fusion) or electrical field (anodic)

•  Not compatible with CMOS low temperature processing

 

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