Technologies
MEMS technology is based on Silicon wafer processing using classical semiconductor processes e.g.
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Thin film deposition (to create conductive, isolating or sacrificial layers, mirrors, etc.) |
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Photolithography (to create pattern to be machined) |
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Surface micro-machining (to create thin structures above the surface) |
and customized MEMS processes e.g.
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Wet chemical etching (KOH) or deep reactive ion etching (DRIE) (to create bulk micro structures) |
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Wafer-to-wafer stacking (functionality combined with wafer scale packaging) |
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Some definitions:
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Micro electro-mechanical systems (MEMS)...
are micro-mechanical structures defined principally in silicon or glass materials. These devices can combine mechanical and/or optical and/or fluidic and electrical elements to provide basic sensing or actuating functions |
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Microsystems (MST)...
are MEMS devices integrated with control electronics, packaged and tested to create a complete sensor or actuator |
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Hybrid microsystems...
are the combination of a MEMS device with other discrete IC devices mounted on a substrate |
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Monolithic microsystems
are standard CMOS IC devices with MEMS functions integrated into the chip | |
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Bulk micromachining
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Surface Micromachining |
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Wafer stacking |
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Used to build mechanical structures where the functionality of the devices are defined within the depth of the wafer (membranes, valves, cantilevers) |
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Encompasses all techniques allowing material to be removed from the bulk of a substrate (e.g. silicon, quartz, silicon on insulator, glass), such as anisotropic wet etching and deep reaction etching |
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True 3-dimensional design potential gives benefits especially for precision applications |
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Distinct processing tools and skills required | |
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Used to build mechanical features (cantilevers, free moving structures) on the surface of a substrate wafer (e.g. silicon, quartz, glass, polymer etc) |
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Successive deposition of sacrificial layers, removal of such layers by etching to release produced structures |
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Processes not largely dissimilar to classical semiconductor processes |
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Commonly integrated with IC process to produce monolothic MEMS |
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Limitations in product performance & stability |
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Used for vacuum level hermetic wafer-scale packaging |
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Two or more wafers of the same or different materials are bonded together
Three level silicon sandwich
Two level: silicon cap on thick
SOI |
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Use of heat and pressure (fusion) or electrical field (anodic) |
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Not compatible with CMOS low temperature processing |
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